Yulia Demyanova

Address:
Yulia Demyanova
Technische Universität Wien
Institut für Logic and Computation 192/4
Favoritenstraße 9–11
1040 Wien
Austria

Room: HE 03 05 (how to get there)
Phone: +43 (1) 58801 – 184 808
Email: ta.etysrofnull@ymed
Web: http://forsyte.at/~demyanova/

Publications

2017
[5] Empirical software metrics for benchmarking of verification tools
Yulia Demyanova, Thomas Pani, Helmut Veith, Florian Zuleger
Formal Methods in System Design, volume 50, number 2-3, pages 289-316, 2017.
[bibtex] [pdf] [doi]
2016
[4] Empirical software metrics for benchmarking of verification tools
Yulia Demyanova, Thomas Pani, Helmut Veith, Florian Zuleger
Software Engineering 2016, Fachtagung des GI-Fachbereichs Softwaretechnik, 23.-26. Februar 2016, Wien, Österreich, pages 67-68, 2016.
[bibtex] [pdf]
2015
[3] Empirical Software Metrics for Benchmarking of Verification Tools
Yulia Demyanova, Thomas Pani, Helmut Veith, Florian Zuleger
Computer Aided Verification - 27th International Conference, CAV 2015, San Francisco, CA, USA, July 18-24, 2015, Proceedings, Part I, pages 561-579, July 2015.
[bibtex] [pdf] [doi]
2013
[2] On the Concept of Variable Roles and its Use in Software Analysis
Yulia Demyanova, Helmut Veith, Florian Zuleger
ArXiv e-prints, volume abs/1305.6745, May 2013.
[bibtex] [pdf]
[1] On the Concept of Variable Roles and its Use in Software Analysis
Yulia Demyanova, Helmut Veith, Florian Zuleger
FMCAD, pages 226-229, 2013.
[bibtex] [pdf]

Latest News

Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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