Research

Fundamental research topics include software model checking, test case generation, static analysis, protocol verification, and formal methods for distributed and concurrent systems. Industrial research is focusing on low level software, and embedded systems in the avionics and automotive sector.

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Teaching

We are offering courses in Formal Methods, Model Checking, Computer-Aided Verification, Abstract Interpretation, and Decision Procedures. We are always looking for enthusiastic young people who are interested in a research project or thesis in the Bachelor, Master, and PhD programs.

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Talks (details)

RiSE seminar
Mateus de Oliveira Oliveira
Some Width Measures for Proofs
Mon, Jun 24 at 16:00
TU Wien, Favoritenstr. 9-11, FAV Hörsaal 2
details
VCLA
Mateus de Oliveira Oliveira
Some Width Measures for Proofs
Mon, Jun 24 at 16:00
FAV Hörsaal 2 (room FAV HS 2), Favoritenstrasse 9-11, 1040, Vienna
details
VCLA
Daniel Le Berre
Recursive Explore and Check Abstraction Refinement (RECAR)
Tue, Jun 18 at 14:00
Library of the Algorithms and Complexity Group, HB 04 08 (Favoritenstrasse 9-11)
details
RiSE seminar
Anne Schreuder
Automatic Synthesis of Polynomial Probabilistic Invariants via Geometric Persistence
Mon, Jun 17 at 10:00
TU Wien, Favoritenstr. 9-11, FAV Hörsaal 2
details
VCLA
Anne Schreuder
Automatic Synthesis of Polynomial Probabilistic Invariants via Geometric Persistence
Mon, Jun 17 at 10:00
FORSYTE/RiSE seminar talk by Mateus de Oliveira Oliveira (U. Bergen, http://unitslice.org/
details
VCLA
Arnaud Durand
Introduction to dependence logic and team semantics
Fri, Jun 07 at 15:00
Seminar Room Gödel, Favoritenstrasse 9-11, Ground Floor, (HB EG 10)
details
VCLA
Colin Toal
Developing software and ML models at IBM, Amazon and integrate.ai
Thu, May 23 at 16:00
Zemanek Seminar Room, Ground Floor, Favoritenstrasse 9-11, 1040 Vienna
details
VCLA
David Basin
Security Protocols: Model Checking Standards
Mon, May 20 at 15:00
FAV Hörsaal 1 (Favoritenstrasse 9-11, ground floor, Vienna 1040)
details
VCLA
Peter Eades
How to Draw a Graph ... Revisited
Tue, Apr 09 at 15:00
EI 4 Reithoffer lecture room, Gußhausstraße 25 (old building), 2nd floor
details
VCLA
Manuel Sorge
Clustered, but when? From static to temporal graph algorithms
Mon, Mar 25 at 11:00
Library of the Algorithms and Complexity Group, HB 04 08 (Favoritenstrasse 9-11)
details
VCLA
Dominik Peters
Truthful Aggregation of Budget Proposals
Tue, Mar 19 at 14:00
FAV 01 C (Seminarraum 188/2), 1. Floor (access via "Stiege 4")
details
VCLA
Stefan Milius
Eilenberg Theorems for Free
Thu, Feb 07 at 11:00
Seminar Room Gödel, Favoritenstrasse 9-11, Ground Floor, (HB EG 10)
details
RiSE seminar
Aleksandar Nanevski
Type and Proof Structures for Concurrent Software Verification
Thu, Aug 16 at 17:00
TU Wien, Favoritenstr. 9-11, Seminarraum Gödel
details
RiSE seminar
Joost-Pieter Katoen
Bayes meets Dijkstra -- Exact Inference by Program Verification
Wed, Jun 06 at 17:00
TU Wien, Seminarraum 127 (Gußhausstr. 25-29 - Stiege 1 - 3.Stock)
details
RiSE seminar
Warren Hunt
Industrial Hardware and Software Verification with ACL2
Wed, May 30 at 17:00
TU Wien, Seminarraum 127 (Gußhausstr. 25-29 - Stiege 1 - 3.Stock)
details
RiSE seminar
Joel Ouaknine
Program Invariants
Tue, May 29 at 15:45
IST, Mondi Seminar Room 2, Central Building
details
RiSE seminar
Alexey Bakhirkin
Towards Fast Parametric Identification for STL
Wed, May 23 at 17:00
IST Austria, Mondi 2
details
RiSE seminar
Stefan Schmid
Polynomial-Time What-If Analysis for Communication Networks: An Automata-Theoretic Approach
Wed, May 09 at 17:00
IST, Mondi 2
details
RiSE seminar
Stefan Ratschan
Counter-example Guided Inductive Synthesis in the Continuous World
Tue, May 08 at 15:00
IST Austria, Mondi 2
details
RiSE seminar
Oded Padon
Deductive verification of distributed protocols in first-order logic
Wed, Apr 18 at 17:00
IST Austria, Mondi 2
details
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