Talks

We regularly host talks in the RiSE seminar and VCLA talks series. The following table summarizes the latest talks in each series – for detailed information or previous talks, please follow the links to the respective websites.

Logo ARiSEVCLA Logo

Martin GroheThe Graph Isomorphism ProblemMon, Nov 05 at 16:00EI 4 Reithoffer lect…details
Marcello D'AgostinoAn informational view of classical logicThu, Oct 25 at 16:30Seminar Room Gödel,…details
Tomi JanhunenWriting Declarative Specifications for ClausesFri, Oct 05 at 14:00Seminar Room Gödel,…details
Rajeev GoreInteractive Synthesis of Verified Vote-counting ProgramsWed, Sep 26 at 16:30Seminar Room Gödel,…details
Toby WalshLiving with Artificial Intelligence – How to stay HumanThu, Sep 20 at 18:00Prechtlsaal, Ground …details
RiSE seminarAleksandar NanevskiType and Proof Structures for Concurrent Software VerificationThu, Aug 16 at 17:00TU Wien, Favoritens…details
Iyad KanjHow to navigate through obstacles?Wed, Jul 25 at 14:00Library, Favoritenst…details
Markus EndresPreference-Aware Database SystemsTue, Jul 24 at 14:00Menger meeting room,…details
Steven ChaplickApproximation Schemes for Geometric Coverage ProblemsThu, Jul 19 at 11:00Library, Favoritenst…details
Torsten SchaubASP in TimeTue, Jun 26 at 09:30Seminar Room Gödel,…details
Ramchandra PhawadeCombining free choice and time in Petri netsFri, Jun 22 at 11:00Library, Favoritenst…details
RiSE seminarJoost-Pieter KatoenBayes meets Dijkstra -- Exact Inference by Program VerificationWed, Jun 06 at 17:00TU Wien, Seminarraum…details
RiSE seminarWarren HuntIndustrial Hardware and Software Verification with ACL2Wed, May 30 at 17:00TU Wien, Seminarraum…details
RiSE seminarJoel OuaknineProgram InvariantsTue, May 29 at 15:45IST, Mondi Seminar R…details
RiSE seminarAlexey Bakhirkin Towards Fast Parametric Identification for STLWed, May 23 at 17:00IST Austria, Mondi 2details
RiSE seminarMelkior OrnikDeception and Unpredictability in Control SystemsWed, May 16 at 17:00IST Austria, Mondi 2details
RiSE seminarStefan SchmidPolynomial-Time What-If Analysis for Communication Networks: An Automata-Theoretic ApproachWed, May 09 at 17:00IST, Mondi 2details
RiSE seminarStefan RatschanCounter-example Guided Inductive Synthesis in the Continuous WorldTue, May 08 at 15:00IST Austria, Mondi 2details
RiSE seminarOded PadonDeductive verification of distributed protocols in first-order logicWed, Apr 18 at 17:00IST Austria, Mondi 2details
RiSE seminarPhilipp RümmerDeciding and Interpolating Algebraic Data Types by ReductionFri, Mar 16 at 10:30TU Wien, HS Zemanek,…details

Latest News

Opening of Vienna Center for Logic and Algorithms (VCLA) on Jan 25

The Vienna Center for Logic and Algorithms is an initiative of the Faculty of Informatics and funded by a three-year competitive grant of Vienna University of Technology. Embedded into the primary research area Computational Intelligence and the funding priority Computational Logic of the Faculty, the center is promoting international scientific collaboration in logic and algorithms. […]

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Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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