Georg Weissenbacher

Georg Weissenbacher

Address:
Georg Weissenbacher
Technische Universität Wien
Institut für Informationssysteme 184/4
Favoritenstraße 9–11
1040 Wien
Austria

Room: HG 03 07 (how to get there)
Phone: +43 (1) 58801 – 184 35
Email: ta.etysrofnull@bnessiew
Web: http://forsyte.at/~weissenbacher/

I’m leading the Rigorous Software Engineering lab of the Formal Methods in Systems Engineering Group. I’ve a master’s level degree from Graz University of Technology and a doctorate in computer science from Oxford University. Prior to my appointment in Vienna, I was a postdoctoral researcher at Princeton University.

My current research on the detection and explanation of Heisenbugs is funded by a Vienna Research Group for Young Investigators grant (stay tuned for publications on that topic).

A list of publications and my curriculum vitae is available from http://www.georg.weissenbacher.science.

Latest News

Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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