Matthias Schlaipfer

Project Assistant

I am currently a PhD student with Prof. Georg Weissenbacher at TU Wien. I graduated with a Dipl.-Ing. degree from TU Graz in 2014 under the supervision of Prof. Roderick Bloem.

My PhD work is in the broad area of program synthesis, programming languages, and proof theory. In this context I have contributed to the GAPT tool developed at TU Wien.

In 2015 I interned at Microsoft Research Cambridge where I worked on optimizing the Datalog engine of the Z3 SMT solver (used for network verification) under supervision of Nuno Lopes.

More recently I interned at Microsoft Research India with Akash Lal and Kaushik Rajan. The work resulting from my internship on optimizing big-data queries using program synthesis has recently been published at SOSP.


[4] Optimizing Big-Data Queries Using Program Synthesis
Matthias Schlaipfer, Kaushik Rajan, Akash Lal, Malavika Samak
Proceedings of the 26th Symposium on Operating Systems Principles, pages 631-646, 2017, ACM.
[bibtex] [pdf] [doi]
[3] Labelled Interpolation Systems for Hyper-Resolution, Clausal, and Local Proofs
Matthias Schlaipfer, Georg Weissenbacher
Journal of Automated Reasoning, 2016, Springer.
[bibtex] [pdf]
[2] Reduction of Resolution Refutations and Interpolants via Subsumption
Roderick Bloem, Sharad Malik, Matthias Schlaipfer, Georg Weissenbacher
Chapter in Hardware and Software: Verification and Testing (Eran Yahav, ed.), volume 8855 of Lecture Notes in Computer Science, pages 188-203, 2014, Springer International Publishing.
[bibtex] [pdf] [doi]
[1] Generalized Reactivity(1) Synthesis without a Monolithic Strategy
Matthias Schlaipfer, Georg Hofferek, Roderick Bloem
Hardware and Software: Verification and Testing - 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers, pages 20-34, 2011.
[bibtex] [pdf] [doi]

Matthias Schlaipfer
Technische Universität Wien
Institut für Logic and Computation 192/4
Favoritenstraße 9–11
1040 Wien

Room: HA 03 09 (how to get there)
Phone: +43 (1) 58801 – 184 901
Email: ta.etysrofnull@refpialhcsm


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Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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