Jens Katelaan

Ph.D. student

I have been a PhD student in the Formal Methods in Systems Engineering group since October 2015. I began my studies under the supervision of Helmut Veith. My current supervisors are Georg Weissenbacher and Florian Zuleger. I am also associated with the LogiCS program (Doktoratskolleg). Before coming to Vienna, I obtained BSc and MSc degrees in computer science at RWTH Aachen University.

My research focus is on the static analysis and formal verification of software. I am particularly interested in logic-based approaches to the (semi-)automatic verification of software with dynamic data structures and/or concurrency.

Address:
Jens Katelaan
Technische Universität Wien
Institut für Logic and Computation 192/4
Favoritenstraße 9–11
1040 Wien
Austria

Room: HA 03 07 (how to get there)
Phone: +43 (1) 58801 – 184 833
Email: ta.etysrofnull@naaletakj
Web: http://forsyte.at/~katelaan/

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Latest News

WWTF ICT project awarded to Igor Konnov

Igor Konnov (PI), together with Josef Widder (co-PI) and Helmut Veith (core team), are awarded an ICT research project APALACHE “Abstraction-based Parameterized TLA Checker” by the Vienna Science and Technology Fund WWTF.

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Austrian Computer Science Day 2015

The Austrian Computer Science Day 2015, which takes place on October 15, features a range of talks by leading Austrian computer scientists, including topics such as computer games, augmented reality, aware systems, semantic web, business processes, and reliable systems. Register for free by October 7, 2015! This year’s speakers are: Alois Ferscha (JKU Linz) Tom […]

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Helmut Veith receives CAV Award

The 2015 CAV Award is given to Edmund Clarke, Orna Grumberg, Ron Hardin, Zvi Harel, Somesh Jha, Robert Kurshan, Yuan Lu, and Helmut Veith for the development and implementation of the localization-reduction technique and the formulation of counterexample-guided abstraction refinement (CEGAR).

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FRIDA’15

We had great talks at FRIDA’15 workshop in Grenoble. The slides of some of the talks are available online.

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