Jens Katelaan

Ph.D. student

I have been a PhD student in the Formal Methods in Systems Engineering group since October 2015. I began my studies under the supervision of Helmut Veith. My current supervisors are Georg Weissenbacher and Florian Zuleger. I am also associated with the LogiCS program (Doktoratskolleg). Before coming to Vienna, I obtained BSc and MSc degrees in computer science at RWTH Aachen University.

My research focus is on the static analysis and formal verification of software. I am particularly interested in logic-based approaches to the (semi-)automatic verification of software with dynamic data structures and/or concurrency.

Address:
Jens Katelaan
Technische Universität Wien
Institut für Logic and Computation 192/4
Favoritenstraße 9–11
1040 Wien
Austria

Room: HA 03 07 (how to get there)
Phone: +43 (1) 58801 – 184 833
Email: ta.etysrofnull@naaletakj
Web: http://forsyte.at/~katelaan/

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Latest News

Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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