Jens Katelaan

Ph.D. student

I have been a PhD student in the Formal Methods in Systems Engineering group since October 2015. I began my studies under the supervision of Helmut Veith. My current supervisors are Georg Weissenbacher and Florian Zuleger. I am also associated with the LogiCS program (Doktoratskolleg). Before coming to Vienna, I obtained BSc and MSc degrees in computer science at RWTH Aachen University.

My research focus is on the static analysis and formal verification of software. I am particularly interested in logic-based approaches to the (semi-)automatic verification of software with dynamic data structures and/or concurrency.

Address:
Jens Katelaan
Technische Universität Wien
Institut für Logic and Computation 192/4
Favoritenstraße 9–11
1040 Wien
Austria

Room: HA 03 07 (how to get there)
Phone: +43 (1) 58801 – 184 833
Email: ta.etysrofnull@naaletakj
Web: http://forsyte.at/~katelaan/

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