Postal Address

Technische Universität Wien
Institut für Informationssysteme 184/4
Arbeitsbereich Formal Methods in Systems Engineering
Favoritenstraße 9–11
1040 Wien

Visiting FORSYTE


We are located at Favoritenstrasse 9–11, 1040 Vienna. The main entrance to our floor is via Staircase 3 (“Stiege 3”) on the third floor of the building. At the door, use the telephone to call the person you’re visiting. More information.


Office hours: Mon-Thu 9:00-11:00
Room: HD 03 19
Phone: +43 (1) 58801 18403
Fax: +43 (1) 58801 18493

Latest News

Winter School on Verification

The Austrian Society for Rigorous Systems Engineering (ARiSE) and the Vienna Center for Logic and Algorithms (VCLA) are organizing a joint winter school on verification at Vienna University of Technology from 6-10 February 2012. Apart from ARiSE/VCLA students, the school will be open to outside students. Details are available from the VCLA website.

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CfP: Workshop on Exploiting Concurrency Efficiently and Correctly (EC^2 2010)

The annual Workshop on Exploiting Concurrency Efficiently and Correctly (EC2) is a forum that brings together researchers working on formal methods for concurrency, and those working on advanced parallel applications. Its goal is to stimulate incubation of ideas leading to future concurrent system design an verification tools that are essential in the multi-core era.

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